{"title":"关于SOI晶圆集成挑战的最后一篇","authors":"W. Loh, Qin Ren","doi":"10.1109/EPTC.2018.8654389","DOIUrl":null,"url":null,"abstract":"In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"19 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"EPIC Via Last on SOI Wafer Integration Challenges\",\"authors\":\"W. Loh, Qin Ren\",\"doi\":\"10.1109/EPTC.2018.8654389\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.\",\"PeriodicalId\":360239,\"journal\":{\"name\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"volume\":\"19 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC.2018.8654389\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2018.8654389","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
