{"title":"基于码相关非线性补偿和段间电流失配校正的12位8GS/s射频采样DAC","authors":"Byeongwoo Koo, SungHan Do, Sang-Gyu Nam, H. Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jungho Lee, Young-Sae Cho, Michael Choi, Jongshin Shin","doi":"10.1109/vlsitechnologyandcir46769.2022.9830442","DOIUrl":null,"url":null,"abstract":"This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET\",\"authors\":\"Byeongwoo Koo, SungHan Do, Sang-Gyu Nam, H. Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jungho Lee, Young-Sae Cho, Michael Choi, Jongshin Shin\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830442\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830442\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET
This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.