{"title":"用于验证IC电源连接的片上检测电路","authors":"H. Manhaeve, Stefaan Kerckenaere","doi":"10.1109/DFTVS.2001.966752","DOIUrl":null,"url":null,"abstract":"Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today's complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device's reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"46 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An on-chip detection circuit for the verification of IC supply connections\",\"authors\":\"H. Manhaeve, Stefaan Kerckenaere\",\"doi\":\"10.1109/DFTVS.2001.966752\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today's complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device's reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use.\",\"PeriodicalId\":187031,\"journal\":{\"name\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"46 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.2001.966752\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966752","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An on-chip detection circuit for the verification of IC supply connections
Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today's complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device's reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use.