{"title":"一种新的基于有源振荡器的自适应频率检测VLSI设计","authors":"M. Sheu, Ho-En Liao, Shr-Shian Yang","doi":"10.1109/APASIC.2000.896924","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel adaptive algorithm to detect the frequency in a noisy environment and its VLSI implementation. The algorithm is computationally efficient since we utilize the special structure of an active oscillator, which results in an adaptive one-coefficient FIR filter realization. A method using the Lagrange multiplier based LMS algorithm is derived for coefficient updating. Based on the proposed algorithm, a high performance VLSI architecture is designed in fixed point operation to reduce the hardware cost. After function simulation, the architecture is implemented by 0.6 /spl mu/m CMOS technology. Its chip area is 2899/spl times/2899 um/sup 2/ and the working frequency is 75 MHz.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A new VLSI design for adaptive frequency-detection based on the active oscillator\",\"authors\":\"M. Sheu, Ho-En Liao, Shr-Shian Yang\",\"doi\":\"10.1109/APASIC.2000.896924\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a novel adaptive algorithm to detect the frequency in a noisy environment and its VLSI implementation. The algorithm is computationally efficient since we utilize the special structure of an active oscillator, which results in an adaptive one-coefficient FIR filter realization. A method using the Lagrange multiplier based LMS algorithm is derived for coefficient updating. Based on the proposed algorithm, a high performance VLSI architecture is designed in fixed point operation to reduce the hardware cost. After function simulation, the architecture is implemented by 0.6 /spl mu/m CMOS technology. Its chip area is 2899/spl times/2899 um/sup 2/ and the working frequency is 75 MHz.\",\"PeriodicalId\":313978,\"journal\":{\"name\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"volume\":\"151 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.2000.896924\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896924","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new VLSI design for adaptive frequency-detection based on the active oscillator
In this paper, we propose a novel adaptive algorithm to detect the frequency in a noisy environment and its VLSI implementation. The algorithm is computationally efficient since we utilize the special structure of an active oscillator, which results in an adaptive one-coefficient FIR filter realization. A method using the Lagrange multiplier based LMS algorithm is derived for coefficient updating. Based on the proposed algorithm, a high performance VLSI architecture is designed in fixed point operation to reduce the hardware cost. After function simulation, the architecture is implemented by 0.6 /spl mu/m CMOS technology. Its chip area is 2899/spl times/2899 um/sup 2/ and the working frequency is 75 MHz.