A self-timed wave pipelined adder using data align method

A 32 bit wave pipelined adder circuitry using static CMOS plus data aligning logic is presented. The self-timed wave pipelining algorithm was implemented in the circuit design. The data aligning logic in the algorithm consisted of the double edge triggered flip-flop detecting the slowest arrived signal, the aligning signal generator and latches. Using the algorithm, the delay variation of the signals at the output of the 32 bit adder could be controlled under 130 ps rather than 766 ps in a conventional adder. The circuit operates at a data rate of 800 M/bps using 0.25 /spl mu/m CMOS technology with a 2.5 V supply voltage.