An SRAM based testing methodology for yield analysis of semiconductor ICs

This work presents a methodology to analyze defects in an SRAM cell based on electrical testing which can help improve yield of semiconductor ICs. It uses an algorithm that utilizes fuzzy logic techniques to post process electrical measurements to analyze the point(s) of failure. To model the impact of opens and shorts in the SRAM cell, a number of resistors were added in various locations in the schematic of a cell where a defect can occur. Simulations were run where these resistors were shorted or opened according to their location(s) and the defect(s) they represent. The work was conducted using 28 nm technology device models. Design and simulations were done using Synopsys transistor level Custom Designer software that includes HSPICE. MATLAB was used to implement the fuzzy logic based algorithm to post process the electrical simulations' results. The algorithm presented in this paper can be modified for different technology nodes and can be used by design and yield engineers in industry.