2xVDD digital output buffer insensitive to process and voltage variations

A 2xVDD output buffer with process and voltage (PV) compensation technique is proposed to keep slew rate (SR) within predefined ranges regardless PV variations. The reason of temperature variation is not considered is that it is found to be relatively low correlated to slew rate for 90 nm process or better. All bias voltages in process and voltage variation detectors are generated from bandgap circuits such that variations have been guaranteed by simulation within less than 4.10%. The data rate is 650/500 MHz given 1.0/2.0 V supply voltage with 20 pF load, respectively, by physical measurements. The Δ SR improvement is 30.7% and 31.4% for 1× VDD and 2× VDD, respectively, when the proposed PV compensation design is activated.