{"title":"一种用于宽带MEMS陀螺仪读出专用集成电路的低通连续delta-sigma接口电路","authors":"Youngtae Yang, Jaehoon Jun, Suhwan Kim","doi":"10.1109/SOCC.2017.8226002","DOIUrl":null,"url":null,"abstract":"This paper presents a low-noise, low-power CMOS interface circuit for MEMS gyroscope readout ASIC. Our interface circuit is composed of a continuous-time delta-sigma modulator, an anti-aliasing filter, and an on-chip reference generator. By using a low-pass delta-sigma modulator instead of a band-pass delta-sigma modulator, a frequency matching circuit is unnecessary which enables wideband operation. A switched-capacitor resistor digital-to-analog converter is exploited to reduce clock jitter sensitivity of the modulator. An anti-aliasing filter rejects the out-band signal, and a low-noise on-chip reference generator is embedded for miniaturization. The proposed circuit is realized in a 0.18 μm CMOS process. It achieves 70.3 dB signal-to-noise ratio in a signal bandwidth from 29.5 kHz to 30.5 kHz with only 0.2 V differential peak-peak input. It dissipates 2.6 mW from a 3.3 V supply.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC\",\"authors\":\"Youngtae Yang, Jaehoon Jun, Suhwan Kim\",\"doi\":\"10.1109/SOCC.2017.8226002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-noise, low-power CMOS interface circuit for MEMS gyroscope readout ASIC. Our interface circuit is composed of a continuous-time delta-sigma modulator, an anti-aliasing filter, and an on-chip reference generator. By using a low-pass delta-sigma modulator instead of a band-pass delta-sigma modulator, a frequency matching circuit is unnecessary which enables wideband operation. A switched-capacitor resistor digital-to-analog converter is exploited to reduce clock jitter sensitivity of the modulator. An anti-aliasing filter rejects the out-band signal, and a low-noise on-chip reference generator is embedded for miniaturization. The proposed circuit is realized in a 0.18 μm CMOS process. It achieves 70.3 dB signal-to-noise ratio in a signal bandwidth from 29.5 kHz to 30.5 kHz with only 0.2 V differential peak-peak input. It dissipates 2.6 mW from a 3.3 V supply.\",\"PeriodicalId\":366264,\"journal\":{\"name\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2017.8226002\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 30th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2017.8226002","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC
This paper presents a low-noise, low-power CMOS interface circuit for MEMS gyroscope readout ASIC. Our interface circuit is composed of a continuous-time delta-sigma modulator, an anti-aliasing filter, and an on-chip reference generator. By using a low-pass delta-sigma modulator instead of a band-pass delta-sigma modulator, a frequency matching circuit is unnecessary which enables wideband operation. A switched-capacitor resistor digital-to-analog converter is exploited to reduce clock jitter sensitivity of the modulator. An anti-aliasing filter rejects the out-band signal, and a low-noise on-chip reference generator is embedded for miniaturization. The proposed circuit is realized in a 0.18 μm CMOS process. It achieves 70.3 dB signal-to-noise ratio in a signal bandwidth from 29.5 kHz to 30.5 kHz with only 0.2 V differential peak-peak input. It dissipates 2.6 mW from a 3.3 V supply.