Henrique Maich, Vladimir Afonso, B. Zatt, L. Agostini, M. Porto
{"title":"HEVC分数运动估计复杂性降低实时应用","authors":"Henrique Maich, Vladimir Afonso, B. Zatt, L. Agostini, M. Porto","doi":"10.1109/LASCAS.2014.6820302","DOIUrl":null,"url":null,"abstract":"This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) - among a total of 24 sizes - to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase in the bit-rate, considering the Y-BD-Rate metric. Based on this evaluation, a simple hardware architecture is proposed to implement the Sum of Absolute Differences (SAD) used in the Fractional Motion Estimation (FME). The proposed architecture is able to calculate SAD with a rate of 30 Full HD (1920×1080) frames per second, requiring a frequency of 1.17GHz. It represents a 63% frequency reduction compared to a scenario where all 24 PU sizes are evaluated.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"HEVC Fractional Motion Estimation complexity reduction for real-time applications\",\"authors\":\"Henrique Maich, Vladimir Afonso, B. Zatt, L. Agostini, M. Porto\",\"doi\":\"10.1109/LASCAS.2014.6820302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) - among a total of 24 sizes - to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase in the bit-rate, considering the Y-BD-Rate metric. Based on this evaluation, a simple hardware architecture is proposed to implement the Sum of Absolute Differences (SAD) used in the Fractional Motion Estimation (FME). The proposed architecture is able to calculate SAD with a rate of 30 Full HD (1920×1080) frames per second, requiring a frequency of 1.17GHz. It represents a 63% frequency reduction compared to a scenario where all 24 PU sizes are evaluated.\",\"PeriodicalId\":235336,\"journal\":{\"name\":\"2014 IEEE 5th Latin American Symposium on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE 5th Latin American Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2014.6820302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2014.6820302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
HEVC Fractional Motion Estimation complexity reduction for real-time applications
This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) - among a total of 24 sizes - to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase in the bit-rate, considering the Y-BD-Rate metric. Based on this evaluation, a simple hardware architecture is proposed to implement the Sum of Absolute Differences (SAD) used in the Fractional Motion Estimation (FME). The proposed architecture is able to calculate SAD with a rate of 30 Full HD (1920×1080) frames per second, requiring a frequency of 1.17GHz. It represents a 63% frequency reduction compared to a scenario where all 24 PU sizes are evaluated.