Transistor Reordering for Electrical Improvement in CMOS Complex Gates

As the automated design of supergates becomes possible, techniques to improve their electrical characteristics grow in relevance. Among the design choices, the order of transistors affects the delay and power dissipation. This paper presents an adaptation of an established transistor reordering algorithm targeting electric gains. The proposed algorithm re-orders using both the probability of the transistor being active and the nature of the transistor's input. Electrical simulations were run for the 4 input P-Class functions, and the proposed algorithm obtains gains in the average power, static power, average delay, and critical delay. Among the logic gates with different designs from the baseline algorithm, the proposed algorithm produced logic gates with smaller power and critical delay in 2146 (63.36%) and 478 (69.38%) of the functions using two design strategies. This paper presents that the transistors' input delay must be considered when reordering transistors for electrical improvement in supergates.