纳米级块体finfet的设计与分析

Jong-Ho Lee, Kyu-Bong Choi, Jongmin Shin
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引用次数: 0

摘要

讨论了14nm块体FinFET的设计,并对其性能进行了物理分析。源漏结深度是减小断流最重要的参数,同时在结深度下方形成峰值浓度大于~2×1018 cm-3的穿通障。均匀体掺杂浓度需要设计为在2~4×1017 cm-3范围内掺杂。源/漏接触电阻可以通过增加源/漏区域的金属接触面积来减小。在VGS-Vth为0.1 V时,栅极氧化物内阱中捕获和发射电子的漏极电流波动小于2%,随着翅片宽度的减小,由于耦合的增加,漏极电流波动略有增加。
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Design and analysis of nano-scale bulk FinFETs
Design of 14 nm bulk FinFET is discussed and some properties are analyzed physically. The source/drain junction depth is the most important parameter to reduce off-current, and a punchthrough barrier of a peak concentration higher than ~2×1018 cm-3 should be formed just underneath the junction depth at the same time. Uniform body doping concentration needs to be designed to have a doping in the range of 2~4×1017 cm-3. The source/drain contact resistance can be reduced by increasing metal contact area on the source/drain region. The drain current fluctuation with the capture and emission of an electron in a trap inside the gate oxide is less than 2% at a VGS-Vth of 0.1 V, and increases slightly due to the increase of coupling as fin width decreases.
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