M. Ma, S. Gunther, B. Greiner, N. Wolff, C. Deutschle, T. Arabi
{"title":"增强未来处理器的热管理","authors":"M. Ma, S. Gunther, B. Greiner, N. Wolff, C. Deutschle, T. Arabi","doi":"10.1109/VLSIC.2003.1221202","DOIUrl":null,"url":null,"abstract":"An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Enhanced thermal management for future processors\",\"authors\":\"M. Ma, S. Gunther, B. Greiner, N. Wolff, C. Deutschle, T. Arabi\",\"doi\":\"10.1109/VLSIC.2003.1221202\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221202\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.
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