Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net wire length minimization should be considered during placement, in addition to the conventional optimization objectives of total area and half perimeter wire length (HPWL). In this paper, we develop effective hierarchical and analytical techniques for high-performance analog circuits placement, which is a complex problem given its multi-objectives and constraints (e.g. hierarchical symmetric groups). The entire circuit is first partitioned hierarchically in a top-down, critical parasitics aware, hierarchical symmetric constraints and proximity constraints feasible manner, where the placement subproblem for each partition at each level can be solved in reasonable run-time. Then, different placement variants are generated for each partition from bottom up, taking advantage of the computation power of modern multi-core systems with parallelization. To assemble the placement variants of different subpartitions, a Mixed Integer Linear Programming (MILP) formulation is proposed which can simultaneously minimize critical parasitic loading, total area and HPWL, and handle hierarchical symmetric constraints, module variants selection and orientation. Experimental results demonstrate the effectiveness of the proposed techniques.