Pascal Cremer, S. Hougardy, Jan Schneider, Jannik Silvanus
Multi patterning technology used in 7nm technology and beyond imposes more and more complex design rules on the layout of cells. The often non local nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for the automatic cell layout that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but simultaneously optimizes the routability of the cell and finds a best folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. In a first step it computes an electrically correct routing using a mixed integer programming formulation. To improve yield and optimize DFM, additional constraints are added to this model. We present experimental results on current 7nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. Our algorithms are currently used for the design of 7nm cells at a leading chip manufacturer where they improved manufacturability and led to reduced turnaround times.
{"title":"Automatic Cell Layout in the 7nm Era","authors":"Pascal Cremer, S. Hougardy, Jan Schneider, Jannik Silvanus","doi":"10.1145/3036669.3036672","DOIUrl":"https://doi.org/10.1145/3036669.3036672","url":null,"abstract":"Multi patterning technology used in 7nm technology and beyond imposes more and more complex design rules on the layout of cells. The often non local nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for the automatic cell layout that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but simultaneously optimizes the routability of the cell and finds a best folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. In a first step it computes an electrically correct routing using a mixed integer programming formulation. To improve yield and optimize DFM, additional constraints are added to this model. We present experimental results on current 7nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. Our algorithms are currently used for the design of 7nm cells at a leading chip manufacturer where they improved manufacturability and led to reduced turnaround times.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117120839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shounak Dhar, M. Iyer, Saurabh N. Adya, L. Singhal, N. Rubanov, D. Pan
In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.
{"title":"An Effective Timing-Driven Detailed Placement Algorithm for FPGAs","authors":"Shounak Dhar, M. Iyer, Saurabh N. Adya, L. Singhal, N. Rubanov, D. Pan","doi":"10.1145/3036669.3036682","DOIUrl":"https://doi.org/10.1145/3036669.3036682","url":null,"abstract":"In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu
Advanced semiconductor process technologies are producing various circuit layout patterns, and it is essential to detect and eliminate problematic ones, which are called lithography hotspots. These hotspots are formed due to light diffraction and interference, which induces complex intrinsic structures within the formation process. Though various machine learning based methods have been proposed for this problem, most of them cannot capture the intrinsic structure of each data. In this paper, we propose a novel feature extraction by representing each data sample in matrix form. We argue that this method can well preserve the intrinsic feature of each sample, leading to better performance.We then further propose a bilinear lithography hotspot detector, which can tackle data in matrix form directly to preserve the hidden structural correlations in the lithography process. Experimental results show that the proposed method outperforms state-of-the-art ones with remarkably large margin in both false alarms and runtime, with 98.16% detection accuracy.
{"title":"Bilinear Lithography Hotspot Detection","authors":"Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu","doi":"10.1145/3036669.3036673","DOIUrl":"https://doi.org/10.1145/3036669.3036673","url":null,"abstract":"Advanced semiconductor process technologies are producing various circuit layout patterns, and it is essential to detect and eliminate problematic ones, which are called lithography hotspots. These hotspots are formed due to light diffraction and interference, which induces complex intrinsic structures within the formation process. Though various machine learning based methods have been proposed for this problem, most of them cannot capture the intrinsic structure of each data. In this paper, we propose a novel feature extraction by representing each data sample in matrix form. We argue that this method can well preserve the intrinsic feature of each sample, leading to better performance.We then further propose a bilinear lithography hotspot detector, which can tackle data in matrix form directly to preserve the hidden structural correlations in the lithography process. Experimental results show that the proposed method outperforms state-of-the-art ones with remarkably large margin in both false alarms and runtime, with 98.16% detection accuracy.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127996920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, D. Pan
Directed self-assembly (DSA) is a promising solution for fabrication of contacts and vias for advanced technology nodes. In this paper, we study a DSA aware detailed routing problem, where DSA guiding pattern assignment and guiding pattern double patterning (DP) compliance are resolved simultaneously. We propose a net planning technique, which pre-routes some nets based on their bounding box positions, to improve both metal layer and via layer qualities. We also introduce a new routing graph model with DSA and DP design rule considerations. The DSA and DP aware detailed routing is then performed based on the net planning result, followed by a post-routing optimization on DSA guiding pattern assignment and decomposition. The experimental result demonstrates that our proposed approach can achieve promising DSA and DP friendly layout, i.e., conflict free on DSA guiding pattern with double patterning assignment for via layer. In addition, our proposed detailed router is able to effectively reduce 20% via number and 15% total wirelength than one recent DSA aware detailed router.
{"title":"DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment","authors":"Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, D. Pan","doi":"10.1145/3036669.3036677","DOIUrl":"https://doi.org/10.1145/3036669.3036677","url":null,"abstract":"Directed self-assembly (DSA) is a promising solution for fabrication of contacts and vias for advanced technology nodes. In this paper, we study a DSA aware detailed routing problem, where DSA guiding pattern assignment and guiding pattern double patterning (DP) compliance are resolved simultaneously. We propose a net planning technique, which pre-routes some nets based on their bounding box positions, to improve both metal layer and via layer qualities. We also introduce a new routing graph model with DSA and DP design rule considerations. The DSA and DP aware detailed routing is then performed based on the net planning result, followed by a post-routing optimization on DSA guiding pattern assignment and decomposition. The experimental result demonstrates that our proposed approach can achieve promising DSA and DP friendly layout, i.e., conflict free on DSA guiding pattern with double patterning assignment for via layer. In addition, our proposed detailed router is able to effectively reduce 20% via number and 15% total wirelength than one recent DSA aware detailed router.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132539348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is a misperception that the Chinese have the same word for crisis as opportunity. Despite that, a technical crisis does present opportunities for researchers and practitioners to solve interesting problems. In this talk we point out two crises: interconnect and runtime, we enumerate interesting physical-synthesis problems arising from these crises, and we discuss the possibility of employing machine learning and hardware acceleration techniques to attack those problems.
{"title":"Interesting Problems in Physical Synthesis","authors":"Pei-Hsin Ho","doi":"10.1145/3036669.3038245","DOIUrl":"https://doi.org/10.1145/3036669.3038245","url":null,"abstract":"It is a misperception that the Chinese have the same word for crisis as opportunity. Despite that, a technical crisis does present opportunities for researchers and practitioners to solve interesting problems. In this talk we point out two crises: interconnect and runtime, we enumerate interesting physical-synthesis problems arising from these crises, and we discuss the possibility of employing machine learning and hardware acceleration techniques to attack those problems.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122626649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a legend story to develop CAD algorithms and CAD/EDA tools for NEC's in-house use is described. About 30 years ago, since there are few commercial CAD tools, ICT vendors had to develop their own CAD tools to enhance the performance of their systems in a short time. Prof. Goto developed several important algorithms for CAD tools and managed to develop many excellent in-house CAD tools. The tools made by him and his apprentices have designed many VLSI/ASIC for NEC's innovative computers and communication systems to enrich our daily lives.
{"title":"The Spirit of in-house CAD Achieved by the Legend of Master \"Prof. Goto\" and his Apprentices","authors":"Yuichi Nakamura","doi":"10.1145/3036669.3038253","DOIUrl":"https://doi.org/10.1145/3036669.3038253","url":null,"abstract":"In this paper, a legend story to develop CAD algorithms and CAD/EDA tools for NEC's in-house use is described. About 30 years ago, since there are few commercial CAD tools, ICT vendors had to develop their own CAD tools to enhance the performance of their systems in a short time. Prof. Goto developed several important algorithms for CAD tools and managed to develop many excellent in-house CAD tools. The tools made by him and his apprentices have designed many VLSI/ASIC for NEC's innovative computers and communication systems to enrich our daily lives.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116766612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Traditionally, there has been a division of labor between computers and humans where all forms of number crunching and bit manipulations are left to computers; whereas, intelligent decision-making is left to us humans. We are now at the cusp of a major transformation that can disrupt this balance. There are two triggers for this: firstly, trillions of connected devices (the "Internet of Things") that have begun to sense and transform the large untapped analog world around us to a digital world, and secondly, (thanks to Moore's Law) beyond-exaflop levels of compute, making a large class of structure learning and decision-making problems now computationally tractable. In this talk, I plan to discuss real challenges and amazing opportunities ahead of us for enabling a new class of applications and services, "Machine Intelligence Led Services". These services are distinguished by machines being in the 'lead' for tasks that were traditionally human-led, simply because computer-led implementations are about to reach and even surpass the quality metrics of current human-led offerings.
{"title":"The Quest for The Ultimate Learning Machine","authors":"P. Dubey","doi":"10.1145/3036669.3038247","DOIUrl":"https://doi.org/10.1145/3036669.3038247","url":null,"abstract":"Traditionally, there has been a division of labor between computers and humans where all forms of number crunching and bit manipulations are left to computers; whereas, intelligent decision-making is left to us humans. We are now at the cusp of a major transformation that can disrupt this balance. There are two triggers for this: firstly, trillions of connected devices (the \"Internet of Things\") that have begun to sense and transform the large untapped analog world around us to a digital world, and secondly, (thanks to Moore's Law) beyond-exaflop levels of compute, making a large class of structure learning and decision-making problems now computationally tractable. In this talk, I plan to discuss real challenges and amazing opportunities ahead of us for enabling a new class of applications and services, \"Machine Intelligence Led Services\". These services are distinguished by machines being in the 'lead' for tasks that were traditionally human-led, simply because computer-led implementations are about to reach and even surpass the quality metrics of current human-led offerings.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131158004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The significantly increased number of routing design rules at sub-20nm nodes has made pin access one of the most critical challenges in detailed routing. Resolving pin access issues in detailed routing stage may be too late due to the fixed pin locations, especially in the area with high pin density. In placement stage when cell movement is allowed, the consideration of pin access has more flexibility. We propose a refinement stage after detailed placement to improve pin access. To respect the given placement solution, the refinement techniques are restricted to cell flipping, same-row adjacent cell swap, and cell shifting. A cost function is presented to model pin access for each pin-to-pin connection. Based on the cost function, two phases are proposed to improve pin access for all the connections simultaneously. In the first phase, we refine the placement by cell flipping and same-row adjacent cell swap. The problem is solved by dynamic programming row by row. In the second phase, only cell shifting is used, and a linear program is formulated to further refine the placement. Experimental results demonstrate that the proposed detailed placement refinement can improve pin access and reduce unroutable nets by about 33% in the detailed routing stage.
{"title":"Pin Accessibility-Driven Detailed Placement Refinement","authors":"Yixiao Ding, C. Chu, Wai-Kei Mak","doi":"10.1145/3036669.3036679","DOIUrl":"https://doi.org/10.1145/3036669.3036679","url":null,"abstract":"The significantly increased number of routing design rules at sub-20nm nodes has made pin access one of the most critical challenges in detailed routing. Resolving pin access issues in detailed routing stage may be too late due to the fixed pin locations, especially in the area with high pin density. In placement stage when cell movement is allowed, the consideration of pin access has more flexibility. We propose a refinement stage after detailed placement to improve pin access. To respect the given placement solution, the refinement techniques are restricted to cell flipping, same-row adjacent cell swap, and cell shifting. A cost function is presented to model pin access for each pin-to-pin connection. Based on the cost function, two phases are proposed to improve pin access for all the connections simultaneously. In the first phase, we refine the placement by cell flipping and same-row adjacent cell swap. The problem is solved by dynamic programming row by row. In the second phase, only cell shifting is used, and a linear program is formulated to further refine the placement. Experimental results demonstrate that the proposed detailed placement refinement can improve pin access and reduce unroutable nets by about 33% in the detailed routing stage.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces popular algorithmic paradigms for circuit placement, presents Goto's classical placement framework based on the generalized force directed relaxation (GFDR) method with an optimal region (OR) formulation and its impacts on modern circuit placement and applications, and provides future placement research directions based on the GFDR and OR formulations.
{"title":"Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement","authors":"Yao-Wen Chang","doi":"10.1145/3036669.3038250","DOIUrl":"https://doi.org/10.1145/3036669.3038250","url":null,"abstract":"This paper introduces popular algorithmic paradigms for circuit placement, presents Goto's classical placement framework based on the generalized force directed relaxation (GFDR) method with an optimal region (OR) formulation and its impacts on modern circuit placement and applications, and provides future placement research directions based on the GFDR and OR formulations.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling. Achieving high performance is always a key index for CPU designs. However, the resistance of interconnects has grown significantly as the dimensions of wires and vias are scaled aggressively. We present novel physical design solutions of the via pillar approach using metal layer promotion and multiple-width configurable wires. This fully automated via pillar design flow mitigates the high resistance impact and becomes indispensable in high performance designs for advanced process technologies. Maintaining power densities while aggressively shrinking chip areas is also a critical requirement, especially for mobile and IoT applications. Lowering supply voltages is one of the most effective means to reducing power consumption, especially for FinFET devices with much lower threshold voltages than planar devices. However, process and timing variation is high even for FinFET devices operating at very low voltages. We present robust ultra-low voltage IP design solutions and the current status and issues of non-Gaussian and asymmetric variation modeling for ultra-low voltage timing signoffs. Finally, advanced chip packaging is presented as a viable solution for integration and system level scaling for complex SOC systems. Specific packaging solutions can meet different requirements of system die and package size, form factor, bandwidth, power and homogeneous or heterogeneous integration. For a silicon-proven system, quantitative advantages of advanced packaging over traditional packaging in silicon thickness, thermal dissipation and voltage drop are presented. Chip packaging integration flow and requirements will also be discussed.
{"title":"Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend","authors":"L. Lu","doi":"10.1145/3036669.3038255","DOIUrl":"https://doi.org/10.1145/3036669.3038255","url":null,"abstract":"In the advanced process technologies of 7nm and beyond, the semiconductor industry faces several new challenges: (1) aggressive chip area scaling with economically feasible process technology development, (2) sufficient performance enhancement of advanced small-scale technology with significantly increased wire and via resistances, (3) power density sustainability with ever shrinking chip area, and (4) advanced chip packaging integration solutions for complex SOC systems. In this presentation, novel physical design solutions of robust IP and design methodologies will be explored to solve these challenges. These innovations are made possible by the co-optimization of process technology, IP design and design flow automation. Density scaling is the most important indicator in the continuation of Moore's law. Before 10nm, chip area reduction is mainly achieved by fundamentally shrinking transistor and metal dimensions. Starting from 7nm, maintaining sufficient and economical scaling is hard to achieve through dimension decrease alone. We present two cost-effective enablers, FIN depopulation and EUV, along with their associated innovative standard cell structures and physical design flows, to realize additional area reduction beyond process dimension scaling. Achieving high performance is always a key index for CPU designs. However, the resistance of interconnects has grown significantly as the dimensions of wires and vias are scaled aggressively. We present novel physical design solutions of the via pillar approach using metal layer promotion and multiple-width configurable wires. This fully automated via pillar design flow mitigates the high resistance impact and becomes indispensable in high performance designs for advanced process technologies. Maintaining power densities while aggressively shrinking chip areas is also a critical requirement, especially for mobile and IoT applications. Lowering supply voltages is one of the most effective means to reducing power consumption, especially for FinFET devices with much lower threshold voltages than planar devices. However, process and timing variation is high even for FinFET devices operating at very low voltages. We present robust ultra-low voltage IP design solutions and the current status and issues of non-Gaussian and asymmetric variation modeling for ultra-low voltage timing signoffs. Finally, advanced chip packaging is presented as a viable solution for integration and system level scaling for complex SOC systems. Specific packaging solutions can meet different requirements of system die and package size, form factor, bandwidth, power and homogeneous or heterogeneous integration. For a silicon-proven system, quantitative advantages of advanced packaging over traditional packaging in silicon thickness, thermal dissipation and voltage drop are presented. Chip packaging integration flow and requirements will also be discussed.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121673679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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