在GaAs/AlGaAs HBTs [F-RISC/G处理器]中实现的500 ps 32 /spl times/ 8寄存器文件

15th Annual GaAs IC Symposium Pub Date : 1993-10-10 DOI:10.1109/GAAS.1993.394497

K. Nah, R. Philhower, H. Greub, J. McDonald

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引用次数: 3

摘要

设计了一种高速寄存器文件，非常适合实现快速但产量有限的技术(如GaAs/AlGaAs HBT)的速度潜力。介绍了所开发的地址驱动电路、写入电路和阈值电压发生器电路。测试策略利用两个线性反馈移位寄存器(lfsr)向寄存器文件提供地址和数据模式。匹配电路验证有效的存储器功能并指示读访问时间。测试结果表明读访问时间为500ps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 500 ps 32 /spl times/ 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

A high speed register file has been designed that is well-suited for achieving the speed potential of a fast but yield-limited technology such as GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two linear feedback shift registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicate a read access time of 500 ps.<>

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15th Annual GaAs IC Symposium

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