一个完全集成的电压调节器在14nm CMOS封装嵌入式空气芯电感具有自修剪,数字控制可变的准时间断导通模式操作

C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De
{"title":"一个完全集成的电压调节器在14nm CMOS封装嵌入式空气芯电感具有自修剪,数字控制可变的准时间断导通模式操作","authors":"C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/ISSCC.2019.8662294","DOIUrl":null,"url":null,"abstract":"Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 \\mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $\\lt/p\\gt\\lt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation\",\"authors\":\"C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De\",\"doi\":\"10.1109/ISSCC.2019.8662294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 \\\\mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $\\\\lt/p\\\\gt\\\\lt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.\",\"PeriodicalId\":265551,\"journal\":{\"name\":\"2019 IEEE International Solid- State Circuits Conference - (ISSCC)\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Solid- State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2019.8662294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2019.8662294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

摘要

具有封装嵌入式空芯电感器[1]或具有平面磁芯的片上螺线管电感器[2]的完全集成电压调节器(FIVR)可在复杂的soc中提供高效的功率输送和细粒度宽范围DVFS,同时提供快速的瞬态响应。FIVR必须在广泛的输出电压和负载电流工作范围内提供高转换效率,包括轻负载到中等负载,以最大限度地提高SoC在不同功率状态下的整体能效。在连续传导模式(CCM)下采用脉宽调制(PWM)控制的高频FIVR设计中,相位脱落和开关标度被用于保持大负载电流的高效率[1-5],脉频调制(PFM)和迟滞控制被用于实现轻到中负载的高效率[3-5]。在本文中,我们提出了一种14nm CMOS的FIVR,其2.5nH空芯电感嵌入超薄无芯封装$(200 μ m$厚)(图8.5.7),具有自调整,软开关和数字控制可变导通时间DCM操作高达70MHz,可在5mA至500mA的轻至中负载电流和0.7-1.2V宽输出电压范围内实现高转换效率。FIVR采用级联编码薄栅极动力总成(图8.5.1),支持高达2Vmax的输入电压,级联编码偏置导轨设置为$V_{in} /2$,轻载时消耗$\lt/p\gt\lt1$ uA。当功率级处于高阻抗状态时,在电感两端连接一个小的厚栅装置来抑制振荡。输出电压由一个响应时间小于ns的比较器监测,当输出低于参考电压时触发电感电流脉冲。采用带有前馈电容的电阻分压器实现快速响应。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation
Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 \mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $\lt/p\gt\lt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
27.2 An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain 22.7 A Programmable Wireless EEG Monitoring SoC with Open/Closed-Loop Optogenetic and Electrical Stimulation for Epilepsy Control 2.5 A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control 11.2 A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range 11.3 A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b-Resolution Capacitance-to-Digital Converter from 1 to 100nF
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1