Khoi-Nguyen Le-Huu, Diem N. Ho, Anh-Vu Dinh-Duc, T. Vu
{"title":"面向32位VLIW DSP处理器内核的RISC指令集架构","authors":"Khoi-Nguyen Le-Huu, Diem N. Ho, Anh-Vu Dinh-Duc, T. Vu","doi":"10.1109/TENCONSPRING.2014.6863068","DOIUrl":null,"url":null,"abstract":"Digital Signal Processors (DSPs), compared to general-purpose processors, have shown their great contribution to the implementation of digital signal processing algorithms such as digital filtering and Fourier analysis. This work deals with the RISC instruction set architecture (ISA) for the 32-bit VLIW Fixed-point DSP processor core proposed in our previous work. The designed DSP has been described in terms of groups of instructions, the opcode maps, and suggested design of the data path based on the proposed ISA. Moreover, advanced and enhanced instructions aimed at audio and image applications will also be presented in this work.","PeriodicalId":270495,"journal":{"name":"2014 IEEE REGION 10 SYMPOSIUM","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Towards a RISC instruction set architecture for the 32-bit VLIW DSP processor core\",\"authors\":\"Khoi-Nguyen Le-Huu, Diem N. Ho, Anh-Vu Dinh-Duc, T. Vu\",\"doi\":\"10.1109/TENCONSPRING.2014.6863068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Digital Signal Processors (DSPs), compared to general-purpose processors, have shown their great contribution to the implementation of digital signal processing algorithms such as digital filtering and Fourier analysis. This work deals with the RISC instruction set architecture (ISA) for the 32-bit VLIW Fixed-point DSP processor core proposed in our previous work. The designed DSP has been described in terms of groups of instructions, the opcode maps, and suggested design of the data path based on the proposed ISA. Moreover, advanced and enhanced instructions aimed at audio and image applications will also be presented in this work.\",\"PeriodicalId\":270495,\"journal\":{\"name\":\"2014 IEEE REGION 10 SYMPOSIUM\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE REGION 10 SYMPOSIUM\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCONSPRING.2014.6863068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE REGION 10 SYMPOSIUM","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCONSPRING.2014.6863068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Towards a RISC instruction set architecture for the 32-bit VLIW DSP processor core
Digital Signal Processors (DSPs), compared to general-purpose processors, have shown their great contribution to the implementation of digital signal processing algorithms such as digital filtering and Fourier analysis. This work deals with the RISC instruction set architecture (ISA) for the 32-bit VLIW Fixed-point DSP processor core proposed in our previous work. The designed DSP has been described in terms of groups of instructions, the opcode maps, and suggested design of the data path based on the proposed ISA. Moreover, advanced and enhanced instructions aimed at audio and image applications will also be presented in this work.
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