{"title":"DDR接口的设计余量方法","authors":"Soujanna Sarkar, A. Brahme, G. Subash Chandar","doi":"10.1109/EPEP.2007.4387151","DOIUrl":null,"url":null,"abstract":"In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design Margin Methodology for DDR Interface\",\"authors\":\"Soujanna Sarkar, A. Brahme, G. Subash Chandar\",\"doi\":\"10.1109/EPEP.2007.4387151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.\",\"PeriodicalId\":402571,\"journal\":{\"name\":\"2007 IEEE Electrical Performance of Electronic Packaging\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Electrical Performance of Electronic Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2007.4387151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2007.4387151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.
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