{"title":"基于FPGA的高分辨率、高帧率图像去失真算法研究","authors":"Yuankai Zeng, Feng Xu, Yunxing Gong, Sijie Huang","doi":"10.1109/ITNEC56291.2023.10082176","DOIUrl":null,"url":null,"abstract":"In order to realize real-time and high-speed distortion removal of camera images, a new improved high resolution and high frame rate image distortion based on FPGA is proposed. The traditional method uses four random access memory (RAM) to buffer the distorted image respectively, and then remaps it with the double rate synchronous dynamic random access memory (DDR), which will cause the system to be unable to process high-resolution images at high frame rates. A new RAM buffer architecture and an interpolation module more suitable for Field Programmable Gate Array (FPGA) implementation are proposed, which can improve the system’s ability to process high-speed and high-resolution distorted images in real time within the acceptable range of resources. Compared with the traditional FPGA de-distortion algorithm, the proposed method can de-distortion with the frame rate of 100 fps and the resolution of 3072 x 2048 x 8bit.","PeriodicalId":218770,"journal":{"name":"2023 IEEE 6th Information Technology,Networking,Electronic and Automation Control Conference (ITNEC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Research on high resolution and high frame rate image de-distortion algorithm based on FPGA\",\"authors\":\"Yuankai Zeng, Feng Xu, Yunxing Gong, Sijie Huang\",\"doi\":\"10.1109/ITNEC56291.2023.10082176\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to realize real-time and high-speed distortion removal of camera images, a new improved high resolution and high frame rate image distortion based on FPGA is proposed. The traditional method uses four random access memory (RAM) to buffer the distorted image respectively, and then remaps it with the double rate synchronous dynamic random access memory (DDR), which will cause the system to be unable to process high-resolution images at high frame rates. A new RAM buffer architecture and an interpolation module more suitable for Field Programmable Gate Array (FPGA) implementation are proposed, which can improve the system’s ability to process high-speed and high-resolution distorted images in real time within the acceptable range of resources. Compared with the traditional FPGA de-distortion algorithm, the proposed method can de-distortion with the frame rate of 100 fps and the resolution of 3072 x 2048 x 8bit.\",\"PeriodicalId\":218770,\"journal\":{\"name\":\"2023 IEEE 6th Information Technology,Networking,Electronic and Automation Control Conference (ITNEC)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-02-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE 6th Information Technology,Networking,Electronic and Automation Control Conference (ITNEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITNEC56291.2023.10082176\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE 6th Information Technology,Networking,Electronic and Automation Control Conference (ITNEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITNEC56291.2023.10082176","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Research on high resolution and high frame rate image de-distortion algorithm based on FPGA
In order to realize real-time and high-speed distortion removal of camera images, a new improved high resolution and high frame rate image distortion based on FPGA is proposed. The traditional method uses four random access memory (RAM) to buffer the distorted image respectively, and then remaps it with the double rate synchronous dynamic random access memory (DDR), which will cause the system to be unable to process high-resolution images at high frame rates. A new RAM buffer architecture and an interpolation module more suitable for Field Programmable Gate Array (FPGA) implementation are proposed, which can improve the system’s ability to process high-speed and high-resolution distorted images in real time within the acceptable range of resources. Compared with the traditional FPGA de-distortion algorithm, the proposed method can de-distortion with the frame rate of 100 fps and the resolution of 3072 x 2048 x 8bit.