{"title":"一个12位150 MS/s 1.5 mW SAR ADC与自适应基数DAC在40纳米CMOS","authors":"Kwuang-Han Chang, C. Hsieh","doi":"10.1109/ASSCC.2016.7844159","DOIUrl":null,"url":null,"abstract":"This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS\",\"authors\":\"Kwuang-Han Chang, C. Hsieh\",\"doi\":\"10.1109/ASSCC.2016.7844159\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.\",\"PeriodicalId\":278002,\"journal\":{\"name\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2016.7844159\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2016.7844159","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS
This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.
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