RAM细胞上VHDL阵列的合成

Proceedings EURO-DAC '92: European Design Automation Conference Pub Date : 1992-11-01 DOI:10.1109/EURDAC.1992.246183

C. Berthet, J. Rampon, L. Sponga

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引用次数: 2

摘要

考虑了VHSIC硬件描述语言(VHDL)综合规范中阵列对象的问题。经验表明，通过合成工具获得的电路不如RAM巨细胞高效。提出了一种新的综合方法，将VHDL阵列映射到RAM原语，并对规范进行了修改。然后将原语映射到THOMSON-TMS CSAM库的RAM生成器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Synthesis of VHDL arrays on RAM cells

The problem of array objects in VHSIC hardware description language (VHDL) specifications for synthesis is considered. Experience shows that circuits obtained by synthesis tools are not as efficient as RAM macrocells. A new synthesis method is proposed that consists in mapping a VHDL array to a RAM primitive, together with a modification of the specification. The primitive is then mapped to a RAM generator of the THOMSON-TMS CSAM Library.<>

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Proceedings EURO-DAC '92: European Design Automation Conference

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