Integration of GBTx emulator with MUCH-XYTER and data processing board for CBM experiment

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) at Darmstadt, Germany. The challenge in CBM experiment is to measure the particles generated in nuclear collisions with unprecedented precision and statistics. To capture the data from each collision a highly time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system that can support high data rate (up to several TB/s). Basic readout chain for CBM consists of a front-end Application Specific Integrated Circuit (ASIC) also known as X-Y Time Energy Read-out (XYTER) ASIC, a radiation hardened high speed optical transceiver board with Gigabit Transceiver (GBTx) ASIC followed by a Data Processing Board (DPB) and First Level Event Selector Interface Board (FLIB). As the first step towards the development of the readout chain, FPGA prototypes of GBTx ASIC and XYTER ASIC also known as GBTx emulator and XYTER emulator are developed. GBTx chips are connected to the XYTER in the front end through Low Voltage Differential Signalling (LVDS) electrical line also known as E-link and in the back-end with DPB using optical fiber. In this work, an FPGA-based readout chain prototype comprising of XYTER emulator, GBTx emulator, and DPB is developed where control and configuration signal of XYTER will be sent from DPB through GBTx emulator. A Python script is written in the computer to generate the control information that will be transferred to DPB through Ethernet using IPBus protocol.