45纳米CMOS技术的背照3d堆叠单光子雪崩二极管

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI:10.1109/IEDM.2017.8268405

Myung-Jae Lee, A. Ximenes, Preethi Padmanabhan, Tzu-Jui Wang, Kuo-Chin Huang, Y. Yamashita, D. Yaung, E. Charbon

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引用次数: 17

摘要

我们报告了世界上第一个45纳米CMOS技术的背照3d堆叠单光子雪崩二极管(SPAD)。该SPAD的暗计数率为55.4cps/μm2，在600nm波长范围内最大光子检测概率为31.8%，在420 ~ 920nm波长范围内最大光子检测概率超过5%，在2.5V偏置电压和室温下的时序抖动为107.7ps。据我们所知，这是任何背光3d堆叠SPAD技术报道过的最好结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology

We report on the world's first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.

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2017 IEEE International Electron Devices Meeting (IEDM)

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