A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control

Performance, leakage and Emin on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44μW at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.