布尔代数与逻辑门

R. Rodrigo
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引用次数: 0

摘要

门级最小化是指找到描述数字电路的布尔函数的最优门级实现的设计任务。在本节中,我们将讨论手动设计的酒窝电路。实现布尔函数的数字逻辑门电路的复杂度直接取决于相应代数表达式的复杂度。虽然函数的真值表表示是唯一的,但它的代数形式可以采用许多不同但等效的形式。用代数方法求布尔函数的极小化是一个棘手的问题。map方法提供了一种结构良好的最小化布尔函数的方法。地图方法也被称为卡诺地图或k-地图方法。由映射得到的简化表达式总是有两种标准形式:乘积和或和的乘积。我们将假设最简单的代数表达式是具有最少数量的项和每个项中尽可能少的字面值的代数表达式。这个表达式产生一个具有最小门数和每个门的最小输入数的电路图。然而,这个最简单的表达式并不是唯一的:有时可能会找到两个或更多满足最小化标准的表达式。在这种情况下,每个解都是令人满意的。
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Boolean Algebra and Logic Gates
Gate-level minimization refers to the design task of finding an optimal gate-level implementation of the Boolean function describing a digital circuit. In this section, we will discuss the manual design of dimple circuits. The complexity of a digital logic-gate circuit that implements a Boolean function directly depends on the complexity of the corresponding algebraic expression. Although the truth-table representation of a function is unique, it algebraic form can take many different, but equivalent, forms. Minimization of Boolean function using the algebraic method is awkward. The map method provides a well-structured method of minimizing Boolean functions. The map method is also known as the Karnaugh map or k-map method. The simplified expression produced by the map are always in two standard forms: sum of products or product of sums. We will assume that the simplest algebraic expression is an algebraic expression with a minimum number of terms and with the smallest possible number of literals in each term. This expression produces a circuit diagram with a minimum number of gates and the minimum number of inputs to each gate. However, this simplest expression is not unique: It is possible to sometimes find two or more expressions that satisfy the minimization criteria. In that case, each solution is satisfactory.
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Fintech and Financial Inclusion Ethics and Governance Sampling and Estimation Boolean Algebra and Logic Gates Emerging Technologies
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