{"title":"一个新的面向性能的模块生成器","authors":"E. Yilmaz, G. Dundar","doi":"10.1109/MIXDES.2006.1706568","DOIUrl":null,"url":null,"abstract":"In this work, a new performance oriented module generator is developed. This software, which has new features such as evaluating a cost function using every possible realization and generating modules according to this data, is part of a more general tool, ALG (analog layout generator) (Balkir, 2003). The new tool supports simple module generation; unfolded and folded transistor generation, as well as capacitance reducing merged structure and mismatch reducing interdigitized and common centroid structures","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"188 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A new performance oriented module generator\",\"authors\":\"E. Yilmaz, G. Dundar\",\"doi\":\"10.1109/MIXDES.2006.1706568\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a new performance oriented module generator is developed. This software, which has new features such as evaluating a cost function using every possible realization and generating modules according to this data, is part of a more general tool, ALG (analog layout generator) (Balkir, 2003). The new tool supports simple module generation; unfolded and folded transistor generation, as well as capacitance reducing merged structure and mismatch reducing interdigitized and common centroid structures\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"188 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706568\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706568","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this work, a new performance oriented module generator is developed. This software, which has new features such as evaluating a cost function using every possible realization and generating modules according to this data, is part of a more general tool, ALG (analog layout generator) (Balkir, 2003). The new tool supports simple module generation; unfolded and folded transistor generation, as well as capacitance reducing merged structure and mismatch reducing interdigitized and common centroid structures
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