VLSI Architecture of Sigmoid Activation Function for Rapid Prototyping of Machine Learning Applications.

This paper presents a novel VLSI architecture design of the Sigmoid activation function using Chebyshev’s polynomial approximation for efficient hardware realization. The Sigmoid activation function is one of the key components for completing the classification task and provides generality to the deep networks. The complexity of the sigmoid function leads to low accuracy and longer latency in dedicated hardware design. Therefore, an accurate and fast hardware architecture of the sigmoid function is explored. Chebyshev’s polynomial approximation method is capable of reducing the sum of products (SOP) terms leading to optimum utilization of available hardware resources in FPGAs. The availability of a large number of embedded array multipliers in new FPGA families like Zynq, Kintex7, Virtex7, etc., makes hardware realization of non-linear functions like sigmoid easier and robust. The proposed VLSI architecture has been implemented and tested for its correctness on Xilinx’s Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2018.3. software platform. It can be further used for any end-to-end prototyping using FPGAs and deployed for high-performance real-time applications.