The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data

Energy is a critical challenge in computing performance. Due to "word size creep" from modern CPUs are inefficient for short-data element processing. We propose and evaluate a new microarchitecture called "Bit-Nibble-Byte"(BnB). We describe our design which includes both long fixed point vectors and as well as novel variable length instructions. Together, these features provide energy and performance benefits on a wide range of applications. We evaluate BnB with a detailed design of 5 vector sizes (128,256,512,1024,2048) mapped into 32nm and 7nm transistor technologies, and in combination with a variety of memory systems (DDR3 and HMC). The evaluation is based on both handwritten and compiled code with a custom compiler built for BnB. Our results include significant performance (19x-252x) and energy benefits (5.6x-140.7x) for short bit-field operations typically assumed to require hardwired accelerators and large-scale applications with compiled code.