一种CMOS低电压高增益运算放大器

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI:10.1109/EDTC.1997.582329

G. Lu, G. Sou

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引用次数: 3

摘要

介绍了一种CMOS自偏置单电源运放。它设计了用于增益增强的调节级联码晶体管和用于互补调节级联码偏置稳定的共模反馈技术。它可以使电源电压降低到约2|V/sub /spl // +2|V/sub / ds，并保持高增益工作。在V/sub dd/=1.8 V时，运算放大器的测量直流增益为115 dB，电容负载为20pf时的单位增益频率为8.6 MHz。

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A CMOS low-voltage, high-gain op-amp

A CMOS, self-biasing, single-supply op amp is presented. It is designed with regulated cascode transistors for gain enhancement and a common-mode feedback technique for bias stabilisation of complementary regulated cascodes. It enables supply voltage lowering to about 2|V/sub /spl tau//|+2|V/sub ds,sat/| with the maintain of high-gain operation. At V/sub dd/=1.8 V, the measured DC gain of the op-amp is 115 dB, with a unity-gain frequency of 8.6 MHz for a capacitive load of 20 pF.

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Proceedings European Design and Test Conference. ED & TC 97

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