一个10位，40 Msamples/s级联折叠和插值A/D转换器，具有宽范围的纠错

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896907

Tae-Hyoung Kim, J. Sung, S. Kim, Woong Joo, Seung-Bin You, Suki Kim

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引用次数: 5

摘要

本文介绍了一种10位、10 m采样率/s的CMOS折叠插值模数转换器(F&I ADC)。提出了一种新的级联结构，以减少比较器的数量和功耗，并增加输入信号的带宽。为了减小采样-保持器(S/H)的非线性误差，采用了电荷泵电路。通过使用大范围的误差校正方案，比较器的宽松设计是可能的。ADC采用0.25 /spl mu/m 1-poly - 5-metal CMOS工艺设计。它以40 Msamples/s的速度消耗62 mW。通过MATLAB预仿真，INL/DNL小于0.5 LSB/0.4 LSB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. To reduce the nonlinear errors in the sample-and-holder (S/H), a charge-pump circuit is used. By using a wide range error correction scheme, the relaxed design of comparators is possible. The ADC was designed using a 0.25 /spl mu/m 1-poly 5-metal CMOS process. It consumes 62 mW at 40 Msamples/s. The INL/DNL is less than 0.5 LSB/0.4 LSB by MATLAB presimulation.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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