{"title":"一个10位分段数字时间转换器,具有10ps级分辨率和偏移校准电路","authors":"Keng-Hong Chu, Tse-An Chen, Chia-Ling Wei","doi":"10.1109/ISNE.2016.7543359","DOIUrl":null,"url":null,"abstract":"A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits\",\"authors\":\"Keng-Hong Chu, Tse-An Chen, Chia-Ling Wei\",\"doi\":\"10.1109/ISNE.2016.7543359\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.\",\"PeriodicalId\":127324,\"journal\":{\"name\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2016.7543359\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543359","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits
A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.