{"title":"采用45纳米技术降低泄漏功率的低功耗3位闪存ADC设计","authors":"J. S. Ubhi, A. Tomar, Mukesh Kumar","doi":"10.1109/ICIST.2018.8426136","DOIUrl":null,"url":null,"abstract":"Most of the signals encountered in real world are analog in nature. Analog-to-digital converters are needed for conversion of an analog signal into digital signal. These converters can be implemented by using different available architectures. The performance of a converter is mainly analyzed based on its speed, area and power. Selection of a particular architecture totally depends upon its application. In this paper, the focus is on dynamic power, static power and delay of an ADC. Threshold Modified Comparator Circuit (TMCC) is used to reduce power dissipation. The work includes use of Self Controllable Voltage Level (SVL) technique to design a flash ADC for reduction of the leakage power. The simulation results of such ADC have been compared at 180 nm and at 45 nm technology. The proposed ADC has 41.12 μW dynamic power dissipation at 10 MHz frequency and 2.12 n W static power dissipation for 1.8 V at 45nm technology node. This data gets reduced to 1.866 μW dynamic power dissipation at the same frequency and static power gets reduced to 119.3 pW for 1.1V at 45nm. The software used for the designing and analysis purpose is Cadence Virtuoso version IC6.1.5.500.14.","PeriodicalId":331555,"journal":{"name":"2018 Eighth International Conference on Information Science and Technology (ICIST)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology\",\"authors\":\"J. S. Ubhi, A. Tomar, Mukesh Kumar\",\"doi\":\"10.1109/ICIST.2018.8426136\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Most of the signals encountered in real world are analog in nature. Analog-to-digital converters are needed for conversion of an analog signal into digital signal. These converters can be implemented by using different available architectures. The performance of a converter is mainly analyzed based on its speed, area and power. Selection of a particular architecture totally depends upon its application. In this paper, the focus is on dynamic power, static power and delay of an ADC. Threshold Modified Comparator Circuit (TMCC) is used to reduce power dissipation. The work includes use of Self Controllable Voltage Level (SVL) technique to design a flash ADC for reduction of the leakage power. The simulation results of such ADC have been compared at 180 nm and at 45 nm technology. The proposed ADC has 41.12 μW dynamic power dissipation at 10 MHz frequency and 2.12 n W static power dissipation for 1.8 V at 45nm technology node. This data gets reduced to 1.866 μW dynamic power dissipation at the same frequency and static power gets reduced to 119.3 pW for 1.1V at 45nm. The software used for the designing and analysis purpose is Cadence Virtuoso version IC6.1.5.500.14.\",\"PeriodicalId\":331555,\"journal\":{\"name\":\"2018 Eighth International Conference on Information Science and Technology (ICIST)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Eighth International Conference on Information Science and Technology (ICIST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIST.2018.8426136\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Eighth International Conference on Information Science and Technology (ICIST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIST.2018.8426136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
现实世界中遇到的大多数信号本质上都是模拟信号。将模拟信号转换为数字信号需要模数转换器。这些转换器可以通过使用不同的可用架构来实现。主要从速度、面积和功率三个方面分析了变换器的性能。特定架构的选择完全取决于它的应用。本文重点讨论了ADC的动态功率、静态功率和时延。采用阈值修正比较电路(TMCC)降低功耗。该工作包括利用自可控电压电平(SVL)技术设计一个闪光ADC,以降低泄漏功率。并对该ADC在180 nm和45 nm工艺下的仿真结果进行了比较。该ADC在10mhz频率下的动态功耗为41.12 μW,在45nm技术节点上1.8 V时的静态功耗为2.12 n W。在相同频率下,动态功耗降为1.866 μW,静态功耗降为119.3 pW,电压为1.1V,波长为45nm。设计分析使用的软件为Cadence Virtuoso版本IC6.1.5.500.14。
Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology
Most of the signals encountered in real world are analog in nature. Analog-to-digital converters are needed for conversion of an analog signal into digital signal. These converters can be implemented by using different available architectures. The performance of a converter is mainly analyzed based on its speed, area and power. Selection of a particular architecture totally depends upon its application. In this paper, the focus is on dynamic power, static power and delay of an ADC. Threshold Modified Comparator Circuit (TMCC) is used to reduce power dissipation. The work includes use of Self Controllable Voltage Level (SVL) technique to design a flash ADC for reduction of the leakage power. The simulation results of such ADC have been compared at 180 nm and at 45 nm technology. The proposed ADC has 41.12 μW dynamic power dissipation at 10 MHz frequency and 2.12 n W static power dissipation for 1.8 V at 45nm technology node. This data gets reduced to 1.866 μW dynamic power dissipation at the same frequency and static power gets reduced to 119.3 pW for 1.1V at 45nm. The software used for the designing and analysis purpose is Cadence Virtuoso version IC6.1.5.500.14.