一个45ns 16×16 CMOS乘法器

Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi
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引用次数: 6

摘要

介绍了一种采用1.5μm设计规则n阱CMOS技术的16 × 16并行乘法器。利用Booth算法和Wallace树约简实现了45ns的乘法时间。典型功耗为100mW。
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A 45ns 16×16 CMOS multiplier
A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.
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