16ns 2K×8b CMOS SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156620

N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada

{"title":"16ns 2K×8b CMOS SRAM","authors":"N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada","doi":"10.1109/ISSCC.1984.1156620","DOIUrl":null,"url":null,"abstract":"This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"198 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 16ns 2K×8b CMOS SRAM\",\"authors\":\"N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada\",\"doi\":\"10.1109/ISSCC.1984.1156620\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"198 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156620\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

本报告将介绍采用1.5μm CMOS技术的2K × 8b SRAM，该SRAM采用硅化铂栅极和单层铝。典型接入时间为16ns, 1MHz时功耗为150mW。

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A 16ns 2K×8b CMOS SRAM

This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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