基于时钟和数据恢复电路的双边采样CES延时锁环

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114500

J. Goh, Yen-Long Lee, Soon-Jyh Chang

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引用次数: 0

摘要

提出了一种基于CDR的双边缘采样时钟嵌入式信令(CES) DLL。该方法结合了双边缘采样和半ui嵌入式时钟编码，与传统的DLL相比，可以节省4倍的延迟单元数，提高了功耗效率，减少了硅面积。测试芯片采用台积电180纳米CMOS工艺设计。测试芯片的核心面积为0.519*0.137 mm2, CDR的功率效率为1.43 mW/Gb/s，工作范围为0.5 Gb/s ~ 3.0 Gb/s。

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A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

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VLSI Design, Automation and Test(VLSI-DAT)

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