HDL逻辑合成中CPU控制器的优化

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606599

G. Yeap

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引用次数: 0

摘要

我们提出了一个在高级描述语言(HDL)逻辑合成环境中优化CPU控制器的程序。该程序对控制器的功率和面积效率进行了优化。将该程序应用于RISC CPU的实际控制器上，与未优化设计相比，我们实现了高达30%的功耗和20%的面积减少。该程序适用于任何在其行为描述中具有符号状态变量的可合成HDL。

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CPU controller optimization in HDL logic synthesis

We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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