用于5G毫米波应用的13dbm输出功率倍频链

Long Wang, Jixin Chen, Debin Hou, Yu Xiang, W. Hong
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引用次数: 0

摘要

本文提出了一种用于5G毫米波应用的输出功率为13dbm、基波抑制为35dbc的倍频链。在实现带外抑制的同时,引入了带通结构,使倍频器和后驱动器之间具有良好的匹配。在倍频链中部署前置和后置驱动器,以降低本振的功率需求,并在二次谐波频段获得高输出功率。测试芯片采用0.13 μ m SiGe BiCMOS工艺,芯尺寸为0.4 mm2。测量表明,在输入功率为2 dBm时,倍增链产生高达13 dBm的输出功率。在28 ~ 36 GHz频段,基频抑制优于35 dBc,三次谐波抑制优于28 dBc。
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A Doubler Chain with 13-dBm Output Power for 5G Millimeter-Wave Application
In this paper, a doubler chain with 13-dBm output power and 35-dBc fundamental rejection is proposed for 5G millimeter-wave application. A bandpass structure is introduced to achieve out-of-band rejection while obtaining a good matching between the doubler and the post-driver. Pre- and post-drivers are deployed in the doubler chain to reduce the power requirement of the local oscillator and obtain high output power at the second harmonic band. The test chip was fabricated in a 0.13-µm SiGe BiCMOS technology with a core size of 0.4 mm2. Measurements show that the doubler chain produces up to 13-dBm out-put power at an input power of 2 dBm. In the frequency band of 28–36 GHz, the fundamental rejection is better than 35 dBc and the third-harmonic rejection is better than 28 dBc.
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