ASIC制程的10b20mps 28mw CMOS ADC

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.722803

A. Wada, K. Tani, Y. Matsushita, Y. Harada

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引用次数: 0

摘要

我们在0.35 /spl mu/m 1-poly - metal ASIC工艺中开发了一个20 Msample/s的10 b CMOS ADC，电源为2.4 V，无需特殊的模拟工艺，由于面积小(4.84 mm/sup 2/)，功耗小，适合嵌入ASIC中。为了实现这个ADC，我们开发了一个两级间放大管道系统和新的剩余放大器电路技术。制作了原型芯片并进行了测试。它显示出良好的线性度，小于/spl plusmn/1 LSB，功耗为28 mW，采样频率为2.4 V，采样频率为20 MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process

We have developed a 20 Msample/s 10 b CMOS ADC with a 2.4 V power supply, in 0.35 /spl mu/m 1-poly 2-Metal ASIC process without a special analog process, which is suitable for embedding in ASICs because of the small area (4.84 mm/sup 2/) and small power consumption. To realize this ADC we have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. The prototype chip was fabricated and was measured. It shows good linearity of less than /spl plusmn/1 LSB and 28 mW power consumption with 2.4 V at 20 MHz sampling.

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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