An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS

Due to the increasing demand of high energy-efficient processor for deep neural networks, traditional neural network accelerators with high-precision weights and activations that usually occupies huge on/off-chip resources with large power consumption is no longer suitable for internet-of-things applications. Binary neural networks (BNNs) reduce memory size and computation complexity, achieving drastically increased energy efficiency. In this paper, an energy-efficient time-domain binary neural network accelerator is optimized for image recognition, with time-domain accumulation (TD-MAC), timing error detection based adaptive voltage scaling design and the related approximate computing. The proposed key features are: 1) an error-tolerant adaptive voltage scaling system with TD-MAC chain truncation for aggressive power reduction, working from near-threshold to normal voltage; 2) architectural parallelism and data reuse with 100% TD-MAC utilization; 3) low power TD-MAC based on analog delay lines. Fabricated in a 28nm CMOS process, our timing error detection based adaptive voltage scaling design enables the whole system achieves a maximum 51.5TOPS/W energy efficiency at 0.42V and 25MHz, with 99.6% accuracy on MNIST dataset.