{"title":"高阶曲率校正CMOS智能温度传感器","authors":"C. Popa","doi":"10.1109/ASDAM.2002.1088545","DOIUrl":null,"url":null,"abstract":"The circuit presented in this paper responds to both of the main requirements of a smart temperature sensor: high performance (that is a very good linearity with respect to temperature variations) and a small price per chip (realized by reducing the die area and the interconnection costs). The core of the proposed smart temperature sensor is represented by an exponential curvature-corrected CMOS bandgap reference, with a temperature coefficient of 7.5 ppm/K for an extended temperature range. The entire circuit was implemented in 0.35 /spl mu/m CMOS technology, the analog core occupying a die area of about 70 /spl mu/m /spl times/ 110 /spl mu/m. In order to reduce the interconnection costs and their delays and static errors, an I/sup 2/C interface was on-chip integrated.","PeriodicalId":179900,"journal":{"name":"The Fourth International Conference on Advanced Semiconductor Devices and Microsystem","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Superior-order curvature-correction CMOS smart temperature sensor\",\"authors\":\"C. Popa\",\"doi\":\"10.1109/ASDAM.2002.1088545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit presented in this paper responds to both of the main requirements of a smart temperature sensor: high performance (that is a very good linearity with respect to temperature variations) and a small price per chip (realized by reducing the die area and the interconnection costs). The core of the proposed smart temperature sensor is represented by an exponential curvature-corrected CMOS bandgap reference, with a temperature coefficient of 7.5 ppm/K for an extended temperature range. The entire circuit was implemented in 0.35 /spl mu/m CMOS technology, the analog core occupying a die area of about 70 /spl mu/m /spl times/ 110 /spl mu/m. In order to reduce the interconnection costs and their delays and static errors, an I/sup 2/C interface was on-chip integrated.\",\"PeriodicalId\":179900,\"journal\":{\"name\":\"The Fourth International Conference on Advanced Semiconductor Devices and Microsystem\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The Fourth International Conference on Advanced Semiconductor Devices and Microsystem\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASDAM.2002.1088545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The Fourth International Conference on Advanced Semiconductor Devices and Microsystem","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASDAM.2002.1088545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Superior-order curvature-correction CMOS smart temperature sensor
The circuit presented in this paper responds to both of the main requirements of a smart temperature sensor: high performance (that is a very good linearity with respect to temperature variations) and a small price per chip (realized by reducing the die area and the interconnection costs). The core of the proposed smart temperature sensor is represented by an exponential curvature-corrected CMOS bandgap reference, with a temperature coefficient of 7.5 ppm/K for an extended temperature range. The entire circuit was implemented in 0.35 /spl mu/m CMOS technology, the analog core occupying a die area of about 70 /spl mu/m /spl times/ 110 /spl mu/m. In order to reduce the interconnection costs and their delays and static errors, an I/sup 2/C interface was on-chip integrated.