系统级封装中并排分立SoC-DRAM配置对SI、PI和热性能的影响

Goeun Kim, Doohee Lim, Jongmin Lee, I. Chang, J. Pak, Youngsang Cho, Yunhyeok Im
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引用次数: 1

摘要

在本文中,在SI(信号完整性),PI(功率完整性)和热性能方面,将SoC(片上系统)- DRAM配置的2D平面并排SiP(系统中封装)与传统的单芯片封装(单芯片封装)进行了比较。在SI和PI方面,DQ信号的孔径宽度被用作性能决策的优劣指标。SiP较短的信道长度和较少的不连续可以导致更大的孔径,但其更长的和更小的PDN(电力输送网络)形状使其变窄。为了提高SiP PI和由此产生的更宽的眼孔径宽度,De-cap(去耦电容)值被扫描,它们的数量、容量和位置被改变。最后,可以找到实现稳健PI性能的最佳De-cap放置。然而,由于SiP配置的SoC与DRAM之间的距离较短,热耦合较大,因此SiP配置的热性能相对较板载SCP差。热比较是基于SoC和DRAM顶部表面的两个温度,以及两个SoC的泄漏功率。通过对星载SCP和SiP协议的比较研究,对如何在数字电视(D-TV)的SiP应用中采用先进的DDR特性有了基本的了解。
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Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance
In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.
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Magnetically Actuated Test Method for Interfacial Fracture Reliability Assessment nSiP(System in Package) Platform for various module packaging applications IEEE 71st Electronic Components and Technology Conference [Title page] Evaluation of Low-k Integration Integrity Using Shear Testing on Sub-30 Micron Micro-Cu Pillars CoW Package Solution for Improving Thermal Characteristic of TSV-SiP for AI-Inference
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