{"title":"无减法AMI与传统AMI的比较","authors":"J. Bucek, R. Lórencz","doi":"10.1109/DDECS.2006.1649585","DOIUrl":null,"url":null,"abstract":"This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The \">\" or \"<\" tests that require either extra clock cycles or extra chip area are completely eliminated","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Comparing Subtraction-Free and Traditional AMI\",\"authors\":\"J. Bucek, R. Lórencz\",\"doi\":\"10.1109/DDECS.2006.1649585\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The \\\">\\\" or \\\"<\\\" tests that require either extra clock cycles or extra chip area are completely eliminated\",\"PeriodicalId\":158707,\"journal\":{\"name\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2006.1649585\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2006.1649585","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The ">" or "<" tests that require either extra clock cycles or extra chip area are completely eliminated