利用设计模块化和重新定位来提高基于fpga的计算系统的生产率

Zbigniew Mudza
{"title":"利用设计模块化和重新定位来提高基于fpga的计算系统的生产率","authors":"Zbigniew Mudza","doi":"10.23919/MIXDES52406.2021.9497564","DOIUrl":null,"url":null,"abstract":"Long development cycles are a crucial disadvantage of FPGA-based systems. Reusing implementation results of a module for multiple instances and across different designs can mitigate this issue. Identical relative placement and routing for multiple instances of a module can be forced in Xilinx 7 Series devices with strict design constraining. A reference instance of a module can be implemented in a certain section of FPGA fabric. Fixed placement and routing constraints can be extracted from the obtained results and relocated to any identical section of FPGA fabric. The approach is especially useful when applied to reconfigurable partitions – it supports independent development and implementation of reconfigurable modules and static design. Also, in some cases it can be extended to relocating entire partial bitstreams.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"383 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Exploiting Design Modularity and Relocation to Increase Productivity in FPGA-based Computing Systems\",\"authors\":\"Zbigniew Mudza\",\"doi\":\"10.23919/MIXDES52406.2021.9497564\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Long development cycles are a crucial disadvantage of FPGA-based systems. Reusing implementation results of a module for multiple instances and across different designs can mitigate this issue. Identical relative placement and routing for multiple instances of a module can be forced in Xilinx 7 Series devices with strict design constraining. A reference instance of a module can be implemented in a certain section of FPGA fabric. Fixed placement and routing constraints can be extracted from the obtained results and relocated to any identical section of FPGA fabric. The approach is especially useful when applied to reconfigurable partitions – it supports independent development and implementation of reconfigurable modules and static design. Also, in some cases it can be extended to relocating entire partial bitstreams.\",\"PeriodicalId\":375541,\"journal\":{\"name\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"volume\":\"383 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/MIXDES52406.2021.9497564\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES52406.2021.9497564","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

开发周期长是基于fpga的系统的一个重要缺点。为多个实例和跨不同设计重用模块的实现结果可以缓解这个问题。在具有严格设计约束的Xilinx 7系列设备中,可以强制对模块的多个实例进行相同的相对放置和路由。模块的参考实例可以在FPGA结构的某个部分中实现。可以从获得的结果中提取固定的放置和路由约束,并将其重新定位到FPGA结构的任何相同部分。这种方法在应用于可重构分区时特别有用——它支持可重构模块和静态设计的独立开发和实现。此外,在某些情况下,它可以扩展到重定位整个部分比特流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Exploiting Design Modularity and Relocation to Increase Productivity in FPGA-based Computing Systems
Long development cycles are a crucial disadvantage of FPGA-based systems. Reusing implementation results of a module for multiple instances and across different designs can mitigate this issue. Identical relative placement and routing for multiple instances of a module can be forced in Xilinx 7 Series devices with strict design constraining. A reference instance of a module can be implemented in a certain section of FPGA fabric. Fixed placement and routing constraints can be extracted from the obtained results and relocated to any identical section of FPGA fabric. The approach is especially useful when applied to reconfigurable partitions – it supports independent development and implementation of reconfigurable modules and static design. Also, in some cases it can be extended to relocating entire partial bitstreams.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC A Simple Method for Analysis of Operation of JLFET THz Radiation Sensors New Monolithic Multi-terminal Si-chips Integrating a Power Converter Phase-leg for Specific Applications Low-noise Amplifier for Photomultiplier Tube Detectors for Plasma Diagnostics Section 6: Embedded Systems
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1