Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497628
G. Jablonski, Piotr Amrozik, K. Hałagan
ARUZ (Analizator Rzeczywistych Układów Złożonych, Analyser of Real Complex Systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows taking into account potential energy barriers in molecular simulations performed on ARUZ and thus modeling thermally-activated diffusion processes in liquids.
ARUZ (analyzer Rzeczywistych Układów Złożonych，分析仪of Real Complex Systems)是位于bionanpark Lodz的大规模并行fpga模拟器。这台机器在硬件上体现了动态点阵液体(DLL)算法。本文给出了DLL功能扩展的FPGA实现细节。这个扩展允许考虑到在ARUZ上进行的分子模拟中的势能障碍，从而模拟液体中的热激活扩散过程。
{"title":"Molecular Simulations Using Boltzmann’s Thermally Activated Diffusion - Implementation on ARUZ – Massively-parallel FPGA-based Machine","authors":"G. Jablonski, Piotr Amrozik, K. Hałagan","doi":"10.23919/MIXDES52406.2021.9497628","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497628","url":null,"abstract":"ARUZ (Analizator Rzeczywistych Układów Złożonych, Analyser of Real Complex Systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows taking into account potential energy barriers in molecular simulations performed on ARUZ and thus modeling thermally-activated diffusion processes in liquids.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115341491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497600
Grzegorz Jaromi, P. Kabacik, Dawid Sysak, R. Makowski
A growing number of flying devices in use results in an increased risk of their collisions. Anti-collision radars for small piloted aircraft are becoming increasingly common. Therefore it is also vital to equip drones, especially those large in size, with such radars.The topic of this paper is the construction of an anti-collision radar for Class 3 drones. A usable model of the hardware, and partly also of the software component, has already been developed. In order to choose the best solution for the software unit in the given class, a programming model of this radar, comprising both the analogue and the digital part, has been prepared. It is of particular importance especially as the large number of possible solutions requires prior modelling and determining the optimal parameter values, mainly when it comes to the emitted signals and echo detection.
{"title":"Structure and Software Elements of Enavi Radar for Large Drones","authors":"Grzegorz Jaromi, P. Kabacik, Dawid Sysak, R. Makowski","doi":"10.23919/MIXDES52406.2021.9497600","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497600","url":null,"abstract":"A growing number of flying devices in use results in an increased risk of their collisions. Anti-collision radars for small piloted aircraft are becoming increasingly common. Therefore it is also vital to equip drones, especially those large in size, with such radars.The topic of this paper is the construction of an anti-collision radar for Class 3 drones. A usable model of the hardware, and partly also of the software component, has already been developed. In order to choose the best solution for the software unit in the given class, a programming model of this radar, comprising both the analogue and the digital part, has been prepared. It is of particular importance especially as the large number of possible solutions requires prior modelling and determining the optimal parameter values, mainly when it comes to the emitted signals and echo detection.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123545625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497623
A. Wojtasik
In recent years, the development of personal computers hardware has been aimed at increasing the number of processor cores. At the same time, the efficiency and reliability of computer interconnecting networks is increased. This enables the introduction and development of parallel and distributed processing methods also in CAD systems. The paper presents the problems related to the parallelization of the computational process and the methods of solving them, based on the example of typical computational experiments used in the design and optimization of integrated circuits topography.
{"title":"Queuing Parallel Computing CAD Tasks in the Design and Optimization of IC Topography","authors":"A. Wojtasik","doi":"10.23919/MIXDES52406.2021.9497623","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497623","url":null,"abstract":"In recent years, the development of personal computers hardware has been aimed at increasing the number of processor cores. At the same time, the efficiency and reliability of computer interconnecting networks is increased. This enables the introduction and development of parallel and distributed processing methods also in CAD systems. The paper presents the problems related to the parallelization of the computational process and the methods of solving them, based on the example of typical computational experiments used in the design and optimization of integrated circuits topography.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126737428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497543
Paweł Pieńczuk, W. Pleskacz, Mateusz Teodorowski
A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.
{"title":"Class AB Operational Amplifier in CMOS 55 nm Technology","authors":"Paweł Pieńczuk, W. Pleskacz, Mateusz Teodorowski","doi":"10.23919/MIXDES52406.2021.9497543","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497543","url":null,"abstract":"A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116273468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497607
R. Kotas, M. Kaminski, W. Tylman, Sebastian Woźniak, M. Wojtera, A. Dąbrowska
The goal of this article is to present the IT platform that was designed and developed for control and monitoring of the thermally active clothing. It consists of several independent components: mobile application, web application, server with a database and data analyzer. First part of the article presents structure and functionalities of the components as well as the communication protocol. Following part of the article presents conducted experiments, preliminary conclusions and future challenges for system authors.
{"title":"Comprehensive Information System for Management of Personalized Protective Thermally Active Clothing","authors":"R. Kotas, M. Kaminski, W. Tylman, Sebastian Woźniak, M. Wojtera, A. Dąbrowska","doi":"10.23919/MIXDES52406.2021.9497607","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497607","url":null,"abstract":"The goal of this article is to present the IT platform that was designed and developed for control and monitoring of the thermally active clothing. It consists of several independent components: mobile application, web application, server with a database and data analyzer. First part of the article presents structure and functionalities of the components as well as the communication protocol. Following part of the article presents conducted experiments, preliminary conclusions and future challenges for system authors.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121955802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497633
M. Jankowski
This paper presents modification of a specialized high-voltage unity-gain buffer related to its physical implementation in a selected high-voltage SOI technology process. Several additional safety devices are required for non- destructive power-up, normal operation and power-down phases of this buffer function cycle. The modifications are largely related to intricacies of the buffer topology, as low- and high-voltage MOS devices are used there in close cooperation. Impact of the implementation-related changes on the buffer operation capabilities is presented and discussed.
{"title":"Implementation of a Modified High-Voltage Unity-Gain Buffer","authors":"M. Jankowski","doi":"10.23919/MIXDES52406.2021.9497633","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497633","url":null,"abstract":"This paper presents modification of a specialized high-voltage unity-gain buffer related to its physical implementation in a selected high-voltage SOI technology process. Several additional safety devices are required for non- destructive power-up, normal operation and power-down phases of this buffer function cycle. The modifications are largely related to intricacies of the buffer topology, as low- and high-voltage MOS devices are used there in close cooperation. Impact of the implementation-related changes on the buffer operation capabilities is presented and discussed.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133991564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497631
{"title":"Section 1: General Invited Papers","authors":"","doi":"10.23919/mixdes52406.2021.9497631","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497631","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131015630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497608
C. Lessi, Vasileios T. Vallindras, Kleanthis V. Hadjisavva, E. Karagianni, G. Deligeorgis, A. Stavrinidis, G. Konstantinidis, A. Panagopoulos
High-electron-mobility transistor (HEMT) is a type of FET fabricated with a junction between two materials with different band gaps. The most common material that is used in HEMT fabrication is based on the Gallium Arsenide hetero- junction (GaAs-AlGaAs). However, Gallium Nitride (GaN) technology is entering dynamically in the area of transistor fabrication because of the high currents’ control by using low voltages. In this paper, a 3D design is presented based on the finger topology. The heterojuction (GaN-AlGaN) creates a piezoelectric polarization and so the two-dimensional electron gas (2DEG), so a full pHEMT model was designed by using Advanced Design System (ADS) software. More specifically, a two-fingers structure is designed in which the two exterior fingers are the source and the one in between is the drain. The transistor size is 160μm length. The small signal model of the designed transistor was created, based on the simulation results. This structure is fabricated and the measured S-parameters are presented.
{"title":"GaN-AlGaN on SiC pHEMT Design for a Digital Radio Frequency Memory","authors":"C. Lessi, Vasileios T. Vallindras, Kleanthis V. Hadjisavva, E. Karagianni, G. Deligeorgis, A. Stavrinidis, G. Konstantinidis, A. Panagopoulos","doi":"10.23919/MIXDES52406.2021.9497608","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497608","url":null,"abstract":"High-electron-mobility transistor (HEMT) is a type of FET fabricated with a junction between two materials with different band gaps. The most common material that is used in HEMT fabrication is based on the Gallium Arsenide hetero- junction (GaAs-AlGaAs). However, Gallium Nitride (GaN) technology is entering dynamically in the area of transistor fabrication because of the high currents’ control by using low voltages. In this paper, a 3D design is presented based on the finger topology. The heterojuction (GaN-AlGaN) creates a piezoelectric polarization and so the two-dimensional electron gas (2DEG), so a full pHEMT model was designed by using Advanced Design System (ADS) software. More specifically, a two-fingers structure is designed in which the two exterior fingers are the source and the one in between is the drain. The transistor size is 160μm length. The small signal model of the designed transistor was created, based on the simulation results. This structure is fabricated and the measured S-parameters are presented.","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/mixdes52406.2021.9497586
{"title":"Section 3: Analysis and Modelling of ICs and Microsystems","authors":"","doi":"10.23919/mixdes52406.2021.9497586","DOIUrl":"https://doi.org/10.23919/mixdes52406.2021.9497586","url":null,"abstract":"","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116952964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-24DOI: 10.23919/MIXDES52406.2021.9497545
M. Brinson, F. Salfelder
The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user-defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated
{"title":"Compact Device Modeling and Simulation with Qucs/Qucs-S/Xyce Modular Libraries","authors":"M. Brinson, F. Salfelder","doi":"10.23919/MIXDES52406.2021.9497545","DOIUrl":"https://doi.org/10.23919/MIXDES52406.2021.9497545","url":null,"abstract":"The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user-defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129732816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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