周期内时钟门控的可疑定时误差预测

Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa
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引用次数: 15

摘要

传统的电路设计是通过增加悲观时间裕度来解决延迟变化问题,从而保证“永远正确”的操作。然而,由于这种最坏情况很少发生,传统的悲观设计方法因此成为设计师实现更高性能和/或超低功耗的主要障碍之一。通过监测电路运行过程中时序误差的发生,自适应时序误差检测和恢复方法作为一种很有前途的解决方案,近年来得到了广泛的关注。作为现有研究的延伸,本文提出了一种用于管道设计性能或能效改进的可疑时序误差预测方法。实验结果表明,与典型余量设计相比,该方法可将吞吐量提高1.41倍,并具有原位定时误差预测能力;2)允许设计超频高达1.88X与“始终正确”输出。
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Suspicious timing error prediction with in-cycle clock gating
Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with “always correct” outputs.
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