Effect of thermal cycling ramp rate on CSP assembly reliability

A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of CSPs for a variety of projects. The experience of the Consortium in building more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and the environmental test results has now been published as a CSP guidelines document. The Consortium assembled fifteen different packages with I/Os from 48 to 784 and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring board (PWB). Another test vehicle was designed and assembled by a team member using their internal resources and was identified as TV-H. The TV-H assemblies were subjected to numerous thermal cycling conditions including -55/spl deg/C to 125/spl deg/C with two ramp rates, one thermal cycle with 2/spl deg/ to 5/spl deg/C/min and the other near thermal shock. Cycles-to-failure (CTF) test results to 1,000 cycles and 400 cycles under these conditions are presented for fine pitch ball grid arrays (FPBGAs), CSPs, and wafer level CSPs (WLCSPs). Decrease in CTFs due to ramp rate and die size increase for different I/O FPBGAs with 0.8 mm pitch are compared and analyzed.