{"title":"用符号模型检验方法进行实际芯片设计中的Bug识别","authors":"Ben Chen, M. Yamazaki, M. Fujita","doi":"10.1109/EDTC.1994.326886","DOIUrl":null,"url":null,"abstract":"We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"46","resultStr":"{\"title\":\"Bug identification of a real chip design by symbolic model checking\",\"authors\":\"Ben Chen, M. Yamazaki, M. Fujita\",\"doi\":\"10.1109/EDTC.1994.326886\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"46\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326886\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bug identification of a real chip design by symbolic model checking
We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips.<>
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