使用基于工程a-IGZO晶体管的2T1C增益单元阵列演示AiMC的多级乘法累积操作

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI:10.1109/IMW56887.2023.10145946

S. Subhechha, S. Cosemans, A. Belmonte, N. Rassoul, S. H. Sharifi, P. Debacker, D. Verkest, R. Delhougne, G. Kar

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引用次数: 0

摘要

我们报告了基于非晶IGZO TFTs的2TlC细胞阵列中多级乘法积累操作的首次演示，用于高效的内存模拟计算(AiMC)实现。讨论并实现了满足目标规格的读写晶体管的器件设计。由于A - igzo TFTs的超低电流(<1.5× 1$0^{-19}$A/$\mu$m)，使得保持时间长，从而实现了多电平操作。

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Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays

We report on the first demonstration of multilevel multiply accumulation operations in 2TlC cell arrays based on amorphous IGZO TFTs for efficient analog in memory compute (AiMC) implementation. Device designs for the read and write transistors to meet the target specifications are discussed and implemented. Multilevel operations are realized thanks to the long retention time enabled by the ultra-low offcurrent (<1.5× 1$0^{-19}$A/$\mu$m) of the a-IGZO TFTs.

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2023 IEEE International Memory Workshop (IMW)

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