RDL Process Development of MEMS Wafer Level Chip Scale Packaging with Silicon Pillar/CuPd as Through Mold Interconnection

This paper is presenting the fabrication of wafer substrate level chip-scale packaging process on MEMS. The key processes are to develop the over-mold wafer level chip-scale packaging solution for MEMS which using metal deposited silicon pillar and Cu/Pd vertical wire as through-mold interconnection (TMI). Wafer level RDL process to route the contact point to UBM bumping pads which going to bond with PCB. The key challenges and process steps are discussed here: Wafer level epoxy molding materials selection; several approaches on molding process optimization; silicon to epoxy molded layers density and thickness ratio control and post mold curing conditions settings were studied to minimize the wafer warpage at <1.5 mm which was induced from CTE mismatch between silicon and epoxy materials. After backgrinding process to reveal the silicon pillar or Cu/Pd vertical wire contact surfaces; subsequent RDL processes are following by physical vapour deposition (PVD) to deposit metal seed layer, electroplating process (ECP) to build the copper metal lines on selective area which isolated by photoresist patterning; spin-coating process with photosensitive materials to build dielectric layers and developed contact/via opening. Process parameters are optimized to control the thermal budget accumulated from each process steps to minimize the wafer warpage within process window. Dielectric and epoxy mold material evaluation results is presented. The electrically test and reliability test was measured to examine the RDL process connection results and reliability.