{"title":"摩尔:从设备扩展到3D集成和系统技术协同优化","authors":"N. Collaert","doi":"10.23919/SNW.2017.8242328","DOIUrl":null,"url":null,"abstract":"In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"More Moore: From device scaling to 3D integration and system-technology co-optimization\",\"authors\":\"N. Collaert\",\"doi\":\"10.23919/SNW.2017.8242328\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.\",\"PeriodicalId\":424135,\"journal\":{\"name\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2017.8242328\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242328","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
More Moore: From device scaling to 3D integration and system-technology co-optimization
In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.
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